'분류 전체보기'에 해당되는 글 695건

원래 32비트로 만들 생각이었지만 테스트 벤치 만들때 너무 귀찮아질 것 같아서 4비트로 만들었다.

실수로 carry랑 temp를 거꾸로 넣어버린 탓에 값이 이상하게 나와서 조금 헤맸다.

한술 더 떠서 Modelsim이 계속 응답 없음을 띄우며 종료되는 현상이 있어서 저장 안하고 몇번씩 거의 다 짠 코드를 날렸다...

Full Adder는 이미 올렸으니 생략하고 나머지만 올린다.

mux2.vhd

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity mux2 is
	port ( mux_a, mux_b : IN std_logic;
		mux_sel : IN std_logic;
		mux_o : OUT std_logic );
end mux2;

architecture arch_mux2 of mux2 is
begin
	process( mux_a, mux_b, mux_sel )
	begin
	case mux_sel is
		when '0' => mux_o <= mux_a;
		when others => mux_o <= mux_b;
	end case;
	end process;
end arch_mux2;

csa.vhd

library ieee;
use ieee.std_logic_1164.all;

entity csa is
	port ( csa_a, csa_b : IN std_logic_vector (3 downto 0);
		csa_cin : IN std_logic;
		csa_s : OUT std_logic_vector (3 downto 0);
		csa_cout : OUT std_logic );
end csa;

architecture arch_csa of csa is
	component fa is
		port ( a, b, cin : IN std_logic;
			s, cout : OUT std_logic );
	end component;

	component mux2 is
		port ( mux_a, mux_b : IN std_logic;
			mux_sel : IN std_logic;
			mux_o : OUT std_logic );
	end component;

	signal temp_0, temp_1 : std_logic_vector (3 downto 0);
	signal carry_0, carry_1 : std_logic_vector (3 downto 0);

	begin
		fa_0 : fa port map ( csa_a(0), csa_b(0), '0', temp_0(0), carry_0(0) );
		fa_cin_0 : for i in 0 to 2 generate
			fa_0 : fa port map ( csa_a(i+1), csa_b(i+1), carry_0(i), temp_0(i+1), carry_0(i+1) );
		end generate;

		fa_1 : fa port map ( csa_a(0), csa_b(0), '1', temp_1(0), carry_1(0) );
		fa_cin_1 : for j in 0 to 2 generate
			fa_1 : fa port map ( csa_a(j+1), csa_b(j+1), carry_1(j), temp_1(j+1), carry_1(j+1) );
		end generate;

		mux_loop : for k in 0 to 3 generate
			mux_0 : mux2 port map ( temp_0(k), temp_1(k), csa_cin, csa_s(k) );
		end generate;

		mux_1 : mux2 port map ( carry_0(3), carry_1(3), csa_cin, csa_cout );
end arch_csa;

csa_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity csa_tb is
end csa_tb;

architecture arch_csa_tb of csa_tb is
	component csa is
		port ( csa_a, csa_b : IN std_logic_vector (3 downto 0);
			csa_cin : IN std_logic;
			csa_s : OUT std_logic_vector (3 downto 0);
			csa_cout : OUT std_logic );
	end component;

	signal input_a, input_b : std_logic_vector ( 3 downto 0 ) := "0000";
	signal input_cin : std_logic;
	signal output_s : std_logic_vector ( 3 downto 0 );
	signal output_cout : std_logic;
	
begin
	csa_port_map : csa port map ( input_a, input_b, input_cin, output_s, output_cout );

	process_a : process
	begin
		input_a <= "0000";
		wait for 10 ns;
		input_a <= "0001";
		wait for 10 ns;
		input_a <= "0010";
		wait for 10 ns;
		input_a <= "0100";
		wait for 10 ns;
		input_a <= "1000";
		wait for 10 ns;

	end process;

	process_b : process
	begin
		wait for 20 ns;
		input_b <= "0111";
	end process;

	process_cin : process
	begin
		input_cin <= '0';
		wait for 5 ns;
		input_cin <= '1';
		wait for 5 ns;
	end process;

end arch_csa_tb;

결과값은 위와 같이 나온다.

input_a와 input_b를 더한 값이 input_s에 저장되며, 만약 자리올림이 발생할 경우 input_cout으로 올림된다.

4bit 를 입력받아 따로 입력된 selector로 선택한 값을 출력해 주는 4 to 1 Multiplexer이다.

왠지 컴파일이 계속 안되다가 며칠 뒤 하니까 된다 (._.

mul4.vhd

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity mux4 is
	port ( a : IN std_logic_vector (3 downto 0);
		s : IN std_logic_vector (1 downto 0);
		o : OUT std_logic );
end mux4;

architecture arch_mux4 of mux4 is
begin
	o <= a(to_integer(unsigned(s)));
end arch_mux4;

mul4_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity mux4_tb is
end mux4_tb;

architecture arch_mux4_tb of mux4_tb is
	component mux4 is
		port ( a : IN std_logic_vector (3 downto 0);
			s : IN std_logic_vector (1 downto 0);
			o : OUT std_logic );
	end component;

	signal input_a : std_logic_vector (3 downto 0);
	signal input_s : std_logic_vector (1 downto 0);
	signal output_o : std_logic;
begin
	mux4_port_map : mux4 port map ( input_a, input_s, output_o );
	
	process_a : process begin
		input_a <= "0110";
		wait for 100 ns;
		input_a <= "1001";
		wait for 100 ns;
	end process;

	process_s : process begin
		input_s <= "00";
		wait for 10 ns;
		input_s <= "01";
		wait for 10 ns;
		input_s <= "10";
		wait for 10 ns;
		input_s <= "11";
		wait for 10 ns;
	end process;
end arch_mux4_tb;