[VHDL] 4 to 1 Multiplexer

4bit 를 입력받아 따로 입력된 selector로 선택한 값을 출력해 주는 4 to 1 Multiplexer이다.

왠지 컴파일이 계속 안되다가 며칠 뒤 하니까 된다 (._.

mul4.vhd

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity mux4 is
	port ( a : IN std_logic_vector (3 downto 0);
		s : IN std_logic_vector (1 downto 0);
		o : OUT std_logic );
end mux4;

architecture arch_mux4 of mux4 is
begin
	o <= a(to_integer(unsigned(s)));
end arch_mux4;

mul4_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity mux4_tb is
end mux4_tb;

architecture arch_mux4_tb of mux4_tb is
	component mux4 is
		port ( a : IN std_logic_vector (3 downto 0);
			s : IN std_logic_vector (1 downto 0);
			o : OUT std_logic );
	end component;

	signal input_a : std_logic_vector (3 downto 0);
	signal input_s : std_logic_vector (1 downto 0);
	signal output_o : std_logic;
begin
	mux4_port_map : mux4 port map ( input_a, input_s, output_o );
	
	process_a : process begin
		input_a <= "0110";
		wait for 100 ns;
		input_a <= "1001";
		wait for 100 ns;
	end process;

	process_s : process begin
		input_s <= "00";
		wait for 10 ns;
		input_s <= "01";
		wait for 10 ns;
		input_s <= "10";
		wait for 10 ns;
		input_s <= "11";
		wait for 10 ns;
	end process;
end arch_mux4_tb;